Field
Embodiments relate to computer architectures. In particular, embodiments relate page faults in computer architectures.
Background Information
Processors commonly execute instructions that access (e.g., read from and/or write to) memory. For example, the instructions may have memory operands that provided addresses of memory locations. A virtual memory management scheme is commonly used in which the instructions indicate virtual or logical memory addresses, which are translated into physical addresses used to access locations in the main memory. Paging is commonly used as a memory-management scheme. Paging organizes the memory into pages. The pages may represent fixed or variable sized blocks or sections of the memory that are handled as individual entities. Accordingly, accesses by the instructions to the memory operands may represent accesses to pages. An advantage of paging is that it allows data to be stored in secondary storage (e.g., a hard disk) and retrieved into main memory when needed.
A page fault may occur when an instruction attempts to access a page that is missing from main memory. For example, the instruction may indicate a virtual address that cannot be mapped to a physical address associated with the page. A page fault may also occur when the access attempted by the instruction is considered impermissible. This may occur, for example, when the instruction attempts to write to a page that is read only. The page fault may effectively represent a fault, interrupt, exception, or trap raised or signaled by hardware (e.g., a processor and/or a memory management unit (MMU)), to software (e.g., an operating system and/or a page fault handler). In response to the page fault, the software (e.g., the page fault handler) may attempt to handle the page fault prior to returning from the page fault back to the processor. Such page faults tend to take a significant amount of time to resolve, tend to reduce performance, and are generally undesirable.
Some instructions have multiple memory operands and attempt to access multiple memory locations. As an example, Intel® Advanced Vector Extensions Programming Reference, document reference number 319433-011, published June 2011, describes several VGATHER instructions (e.g., VGATHERDPD, VGATHERQPD, VGATHERDPS, VGATHERQPS, VPGATHERDD, VPGATHERQD, VPGATHERDQ, and VPGATHERQQ). The VGATHER instructions are used to gather or load multiple values from memory using memory addresses derived from a vector of indexes. By way of example, VPGATHERDD/VPGATHERQD is able to gather up to up to 4 or 8 values from memory. Other instructions that have two or more memory operands and attempt to access two or more memory locations are known in the art.
FIG. 1 is a block diagram illustrating an example gather operation 100 that may be performed responsive to a VGATHER instruction 101 that specifies multiple memory addresses 102 of multiple corresponding pages 103 in memory 104. The VGATHER operation gathers or loads eight values from eight pages using eight corresponding memory addresses specified by the VGATHER instruction and stores them in result packed data 104. For example, a first memory address 0 102-0 corresponds to a first page 0 103-0, a second memory address 1 102-1 corresponds to a second page 1 103-1, and so on. Accordingly, the VGATHER instruction potentially attempts to simultaneously access up to eight different pages. Such a VGATHER instruction/operation may be used, for example, when transposing a large matrix, or otherwise accessing sparse memory locations.
A significant problem may occur when two or more, or worse all eight, of the pages indicated by the VGATHER instruction are missing from the memory and/or when the accesses to the pages are impermissible. In particular, execution of the VGATHER instruction may involve two or more, or worse potentially eight, sequential page faults. The current page fault mechanism for VGATHER is sequential, with right-to-left address ordering of the page faults. For example, if during the execution of the VGATHER instruction, the pages corresponding to memory address 0, memory address 2, and memory address 7 are not present in physical memory, then a first page fault may be raised for memory address 0. After the first page fault has been resolved, execution of the VGATHER instruction may be restarted and a second page fault may be raised for memory address 2. After the second page fault has been resolved, execution of the VGATHER instruction may be restarted and a third page fault may be raised for memory address 7. In some cases, up to eight sequential page faults may be raised for such a VGATHER instruction. Similarly, various other instructions may specify two or more memory addresses which may potentially lead to two or more sequential page faults being raised.
Sequential resolution of such page faults may tend to take a significant amount of time to resolve, tend to reduce performance, and is generally undesirable.